A variety of applications have been developed wherein it is desirable to utilize a non-volatile integrated circuit (semiconductor) memory device that is electrically erasable and programmable but which does not require a refresh of stored data. Research has further been directed to providing an increase in storage capacitance and integrity of data storage in such non-volatile memory devices. One example of non-volatile memory devices that may provide large capacity and high data integrity without refresh of the stored data is a NAND-type flash memory device. Because data is maintained even when power is turned off, such flash memory devices have been widely used in a variety of electronic devices (e.g., hand held terminals, portable computers, etc.) where there is a risk of unexpected power loss (such as from turning off the device).
In such non-volatile memory devices, Incremental Step Pulse Programming (ISPP) has been used in order to control a program voltage profile. According to this programming method, a program voltage (also referred to herein as a word line voltage) is increased stepwise depending on a repetition of program loops of a program cycle. As is well-known, the program loops include a program section and a program verification section. The program voltage is increased by pre-set increments. In accordance with the above-mentioned ISPP mode, a threshold voltage of a cell programmed in a program operation may be increased by one or more increments set in the program loops. In order to narrow a threshold voltage profile of a finally programmed cell, it may be desirable to set an increment of a program voltage. The smaller the increment of the program voltage is, the larger the a number of a program loops a program cycle may have. Accordingly, the number of the program loops may be determined to obtain the most suitable threshold voltage profile without unduly limiting a performance of a memory device.
Circuits for generating program voltages according to ISPP mode are disclosed in U.S. Pat. No. 5,642,309 entitled “Auto-Program Circuit In A Nonvolatile Semiconductor Memory Device” and U.S. Pat. No. 6,469,933 entitled “Flash Memory Device Capable of Preventing Program Disturb and Method for Programming the Same”, assigned to the assignee of the present invention, the disclosures of which are hereby incorporated herein by reference in their entirety as if set forth fully herein. The programming voltages may be generated by a voltage divider that is connected to an output node, as denoted by 36 in FIG. 1 of the '309 patent.
In non-volatile memory devices, multi-level data (also referred to as “multi-bit data”) or single-level data (also referred to as “single-bit data”) may be stored in one memory cell. It may be desirable to differently set an increment of a word line voltage used in programming the multi-level data (also referred to as a multi-level program mode) and an increment of a word line voltage used in programming the single-level data (also referred to as a single-level program mode). For example, word line voltages may increase as much as 0.2V every program loop in programming multi-level data. In contrast, word line voltages may increase as much as 0.8V every program loop in programming single-level data. In order to increase word line voltages, a voltage divider is provided in a word line generator circuit. An example of a voltage divider for a single mode non-volatile memory device is shown in FIG. 1 of the above-mentioned U.S. Pat. No. 5,642,309. A multilevel non-volatile memory device is described in U.S. Pat. No. 6,067,248 entitled “Nonvolatile Semiconductor Memory With Single-Bit and Multi-Bit Modes of Operation and Method for Performing Programming and Reading Operations Therein”, assigned to the assignee of the present invention, the disclosure of which is hereby incorporated herein by reference in its entirety as if set forth fully herein.